Vitajte na EDABoard.com! Medzinárodné elektronické diskusné fórum: softvér EDA, obvody, schémy, knihy, teória, dokumenty, asic, pld, 8051, DSP, sieť, RF, analógový dizajn, PCB, servisné príručky

Register Log in

FPGAdv navhr schemy - kodovy zamok a klopny obvod JK problem

skorec1

New member
FPGAdv navhr schemy - kodovy zamok a klopny obvod JK problem
Zdravim, vedel by mi niekto poradit? spravil som logicku schemu kodovy zamok cez klopny obvod D a JK ale pre JK zrejme niekde robim chybu, nevie niekto porait?

valal.sk/upload/savefile_php/uploads/ea3fd47564.png

tu je schema a chyba ktoru mi hlasi...

a tu je kod schemy VHDL v FPGAdv
Code:
-- VHDL Entity zamok_skovran_lib.blokova_schema_JK.symbol
--
-- Created:
--          by - Skorec.UNKNOWN (SKOREC-PC)
--          at - 23:01:33 12. 12. 2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY blokova_schema_JK IS
   PORT( 
      a     : IN     std_logic;
      b     : IN     std_logic;
      clk   : IN     std_logic;
      reset : IN     std_logic;
      sig1  : IN     std_logic;
      Ya    : OUT    std_logic;
      Yb    : OUT    std_logic
   );

-- Declarations

END blokova_schema_JK ;

--
-- VHDL Architecture zamok_skovran_lib.blokova_schema_JK.struct
--
-- Created:
--          by - Skorec.UNKNOWN (SKOREC-PC)
--          at - 23:01:33 12. 12. 2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ARCHITECTURE struct OF blokova_schema_JK IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL a_non : std_logic;
   SIGNAL b_non : std_logic;
   SIGNAL j     : std_logic;
   SIGNAL j1    : std_logic;
   SIGNAL k     : std_logic;
   SIGNAL k1    : std_logic;
   SIGNAL k2    : std_logic;
   SIGNAL p     : std_logic_vector(1 TO 3);
   SIGNAL p_non : std_logic_vector(1 TO 3);


   -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'jkff'
   SIGNAL mw_U_0reg_cval : std_logic;

   -- ModuleWare signal declarations(v1.9) for instance 'U_3' of 'jkff'
   SIGNAL mw_U_3reg_cval : std_logic;

   -- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'jkff'
   SIGNAL mw_U_5reg_cval : std_logic;


BEGIN

   -- ModuleWare code(v1.9) for instance 'U_9' of 'and'
   Ya <= p_non(1) AND p_non(2) AND p(3);

   -- ModuleWare code(v1.9) for instance 'U_14' of 'and'
   Yb <= p(1) AND p_non(2) AND p(3);

   -- ModuleWare code(v1.9) for instance 'U_21' of 'and'
   j1 <= a_non AND b AND p_non(1) AND p_non(3);

   -- ModuleWare code(v1.9) for instance 'U_22' of 'and'
   k <= a_non AND b AND p_non(3);

   -- ModuleWare code(v1.9) for instance 'U_23' of 'and'
   k2 <= a_non AND b AND p(1) AND p(2);

   -- ModuleWare code(v1.9) for instance 'U_1' of 'inv'
   b_non <= NOT(b);

   -- ModuleWare code(v1.9) for instance 'U_2' of 'inv'
   a_non <= NOT(a);

   -- ModuleWare code(v1.9) for instance 'U_0' of 'jkff'
   p(1) <= mw_U_0reg_cval;
   p_non(1) <= NOT(mw_U_0reg_cval);
   u_0seq_proc: PROCESS (clk, reset)
   BEGIN
      IF (reset = '1') THEN
         mw_U_0reg_cval <= '0';
      ELSIF (clk'EVENT AND clk='1') THEN
         IF ((j = '0') AND (k = '0')) THEN
            mw_U_0reg_cval <= mw_U_0reg_cval;
         ELSIF ((j = '0') AND (k = '1')) THEN
            mw_U_0reg_cval <= '0';
         ELSIF ((j = '1') AND (k = '0')) THEN
            mw_U_0reg_cval <= '1';
         ELSIF ((j = '1') AND (k = '1')) THEN
            mw_U_0reg_cval <= NOT(mw_U_0reg_cval);
         END IF;
      END IF;
   END PROCESS u_0seq_proc;

   -- ModuleWare code(v1.9) for instance 'U_3' of 'jkff'
   p(2) <= mw_U_3reg_cval;
   p_non(2) <= NOT(mw_U_3reg_cval);
   u_3seq_proc: PROCESS (clk, reset)
   BEGIN
      IF (reset = '1') THEN
         mw_U_3reg_cval <= '0';
      ELSIF (clk'EVENT AND clk='1') THEN
         IF ((j1 = '0') AND (k1 = '0')) THEN
            mw_U_3reg_cval <= mw_U_3reg_cval;
         ELSIF ((j1 = '0') AND (k1 = '1')) THEN
            mw_U_3reg_cval <= '0';
         ELSIF ((j1 = '1') AND (k1 = '0')) THEN
            mw_U_3reg_cval <= '1';
         ELSIF ((j1 = '1') AND (k1 = '1')) THEN
            mw_U_3reg_cval <= NOT(mw_U_3reg_cval);
         END IF;
      END IF;
   END PROCESS u_3seq_proc;

   -- ModuleWare code(v1.9) for instance 'U_5' of 'jkff'
   p(3) <= mw_U_5reg_cval;
   p_non(3) <= NOT(mw_U_5reg_cval);
   u_5seq_proc: PROCESS (clk, reset)
   BEGIN
      IF (reset = '1') THEN
         mw_U_5reg_cval <= '0';
      ELSIF (clk'EVENT AND clk='1') THEN
         IF ((sig1 = '0') AND (k2 = '0')) THEN
            mw_U_5reg_cval <= mw_U_5reg_cval;
         ELSIF ((sig1 = '0') AND (k2 = '1')) THEN
            mw_U_5reg_cval <= '0';
         ELSIF ((sig1 = '1') AND (k2 = '0')) THEN
            mw_U_5reg_cval <= '1';
         ELSIF ((sig1 = '1') AND (k2 = '1')) THEN
            mw_U_5reg_cval <= NOT(mw_U_5reg_cval);
         END IF;
      END IF;
   END PROCESS u_5seq_proc;

   -- ModuleWare code(v1.9) for instance 'U_4' of 'or'
   j <= a OR b_non OR p(3);

   -- ModuleWare code(v1.9) for instance 'U_8' of 'or'
   k1 <= a_non OR b OR p(1);

   -- Instance port mappings.

END struct;
 
Toggle Sidebar

Welcome to EDABoard.com

Sponsor

Top