ako vybudovať dva dual port RAM?

[lzh08]

ako sa stavia dva dual port RAM použitím M4K?
Chcem používať M4K na výstavbu dvoch dual port RAM, z ktorých každý obsahuje dual port RAM 64k bit, celkom je 128k bitov.

Toto je správa za kompilácii.
Total Memory bitov: 65536/239216.
Prečo? Myslím, že výsledok by mal byť 131072/239216.
ako sa stavia dva dual port RAM?
použitie "vytvárať"?
--- Kód
IEEE.STD_LOGIC_1164.all použitie;
IEEE.STD_LOGIC_ARITH.all použitie;
IEEE.STD_LOGIC_UNSIGNED.all použitie;

jednotka je dualportram
prístav
(
clk: in std_logic;
dout: InOut std_logic_vector (7 downto 0)
);
koniec dualportram;

architektúra akcie je dualportram

zložka lpmramdp_1
PORT
(
data: IN std_logic_vector (15 downto 0);
oriešok: IN std_logic: = '1 ';
wraddress: IN std_logic_vector (11 downto 0);
rdaddress: IN std_logic_vector (12 downto 0);
Hodiny: IN std_logic;
q: out std_logic_vector (7 downto 0)
);
koniec zložky;

zložka lpmramdp_2
PORT
(
data: IN std_logic_vector (15 downto 0);
oriešok: IN std_logic: = '1 ';wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0); rdaddress: IN std_logic_vector (12 downto 0);
Hodiny: IN std_logic;
q: out std_logic_vector (7 downto 0)
);
koniec zložky;

signálu wrCount_1: std_logic_vector (11 downto 0);
signálu rdCount_1: std_logic_vector (12 downto 0);
signálu dataIn_1: std_logic_vector (15 downto 0);
signálu wrCount_2: std_logic_vector (11 downto 0);
signálu rdCount_2: std_logic_vector (12 downto 0);
signálu dataIn_2: std_logic_vector (15 downto 0);
- Signál dataOut: std_logic_vector (7 downto 0);

začať
process (CLK)
začať
Ak rising_edge (CLK) then
wrCount_1 <= wrCount_1 1;
rdCount_1 <= rdCount_1 1;
wrCount_2 <= wrCount_2 1;
rdCount_2 <= rdCount_2 1;
end if;
end process;

u1: lpmramdp_1
port map
(
data => dataIn_1,
oriešok => '1 ',
wraddress => wrCount_1,
rdaddress => rdCount_1,
hodiny => clk,
q => dout
);

U2: lpmramdp_2
port map
(
data => dataIn_2,
oriešok => '1 ',
wraddress => wrCount_2,
rdaddress => rdCount_2,
hodiny => clk,
q => dout
);
end;

 

[jcchan]

To use synplicity to synthesis