Need to understand a mux implementation in verilog code...

V

VMSK

Guest
I am looking at a verilog code written by someone else . Below is the snippet .

module test( ……. )
Input TMS,
`define STATE_1 4\'b0100
`define STATE_2 4\'b0101
reg [3:0] NxtState;
wire [3:0] CurState;

always @* begin
case (CurState[3:0])
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;
default : NxtState[3:0] = {4{1\'bx}};
endcase
End

endmodule



The is not the full code , I have just taken some parts of it to ask question.
Wanted to understand what is happening in :
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;

Thanks,
Supritha
 
On Friday, March 31, 2023 at 2:15:28 AM UTC-4, VMSK wrote:
I am looking at a verilog code written by someone else . Below is the snippet .

module test( ……. )
Input TMS,
`define STATE_1 4\'b0100
`define STATE_2 4\'b0101
reg [3:0] NxtState;
wire [3:0] CurState;

always @* begin
case (CurState[3:0])
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;
default : NxtState[3:0] = {4{1\'bx}};
endcase
End

endmodule



The is not the full code , I have just taken some parts of it to ask question.
Wanted to understand what is happening in :
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;

Thanks,
Supritha
Click to expand...

The verilog expression x ? a : b is a selector, like a mux. X is the selection control. a and b are the input being selected. STATE_1 and STATE_2 are constants. I don\'t know what `STATE_1 means, or even `define. Having `STATE_1 at the beginning of a line is odd.

Is this construct in any of your Verilog texts?

I\'m wondering if \'define is like the define in C where it tells a pre-processor to make a text substitution?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
 
On 3/31/2023 2:15 AM, VMSK wrote:
I am looking at a verilog code written by someone else . Below is the snippet .

module test( ……. )
Input TMS,
`define STATE_1 4\'b0100
`define STATE_2 4\'b0101
reg [3:0] NxtState;
wire [3:0] CurState;

always @* begin
case (CurState[3:0])
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;
default : NxtState[3:0] = {4{1\'bx}};
endcase
End

endmodule



The is not the full code , I have just taken some parts of it to ask question.
Wanted to understand what is happening in :
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;
Click to expand...

Substituting the `defines:

4\'b0100 : NxtState[3:0] = TMS ? 4\'b0100 : 4\'b0101;

I believe this would translate in English to:

If CurState[3:0] = 4\'b0100 then
if NxtState{3:0] = TMS then 4\'b0100 = 4\'b0100, else 4\'b0100 = 4\'b0101.


This doesn\'t make any sense to me because the use of `define for STATE_1
and STATE_2 just means that the 4 bit binary will be replaced with the
defined value.

Charlie







 
On 4/1/2023 10:36 AM, Charlie wrote:
On 3/31/2023 2:15 AM, VMSK wrote:
I am looking at a verilog code written by someone else . Below is the
snippet .

module test( ……. )
Input TMS,
  `define STATE_1  4\'b0100
  `define STATE_2  4\'b0101
reg                                 [3:0]     NxtState;
  wire                                [3:0]     CurState;

always @* begin
        case (CurState[3:0])
           `STATE_1  : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;
            default : NxtState[3:0] = {4{1\'bx}};
        endcase
End

endmodule



The is not the full code , I have just taken some parts of it to ask
question.
Wanted to understand what is happening in :
  `STATE_1  : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;

Substituting the `defines:

4\'b0100 : NxtState[3:0] = TMS ? 4\'b0100 : 4\'b0101;

I believe this would translate in English to:

If CurState[3:0] = 4\'b0100 then
if NxtState{3:0] = TMS then 4\'b0100 = 4\'b0100, else 4\'b0100 = 4\'b0101.


This doesn\'t make any sense to me because the use of `define for STATE_1
and STATE_2 just means that the 4 bit binary will be replaced with the
defined value.

Charlie
Click to expand...

Correction, I misread the whole thing:

It should be read as:

If CurState[3:0] = 4\'b0100 then
NxtState[3:0] = 4\'b0100 if TMS = 4\'b0100 else NxtState[3:0] = 4\'b0101.

Which makes more sense.

Charlie



 
On Saturday, April 1, 2023 at 10:52:12 AM UTC-4, Charlie wrote:
On 4/1/2023 10:36 AM, Charlie wrote:
On 3/31/2023 2:15 AM, VMSK wrote:
I am looking at a verilog code written by someone else . Below is the
snippet .

module test( ……. )
Input TMS,
`define STATE_1 4\'b0100
`define STATE_2 4\'b0101
reg [3:0] NxtState;
wire [3:0] CurState;

always @* begin
case (CurState[3:0])
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;
default : NxtState[3:0] = {4{1\'bx}};
endcase
End

endmodule



The is not the full code , I have just taken some parts of it to ask
question.
Wanted to understand what is happening in :
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;

Substituting the `defines:

4\'b0100 : NxtState[3:0] = TMS ? 4\'b0100 : 4\'b0101;

I believe this would translate in English to:

If CurState[3:0] = 4\'b0100 then
if NxtState{3:0] = TMS then 4\'b0100 = 4\'b0100, else 4\'b0100 = 4\'b0101.


This doesn\'t make any sense to me because the use of `define for STATE_1
and STATE_2 just means that the 4 bit binary will be replaced with the
defined value.

Charlie

Correction, I misread the whole thing:

It should be read as:
If CurState[3:0] = 4\'b0100 then
NxtState[3:0] = 4\'b0100 if TMS = 4\'b0100 else NxtState[3:0] = 4\'b0101.

Which makes more sense.
Click to expand...

You have the selection expression a bit wrong. It would be
if (TMS) then
NxtState[3:0] = 4\'b0100
else
NxtState[3:0] = 4\'b0101

I don\'t recall exactly the values of TMS that equate to true and false for TMS, but I expect you get the idea.

I didn\'t read the code carefully enough to see the case statement. I must be getting old or something.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209
 
On 4/1/2023 12:33 PM, gnuarm.del...@gmail.com wrote:
On Saturday, April 1, 2023 at 10:52:12 AM UTC-4, Charlie wrote:
On 4/1/2023 10:36 AM, Charlie wrote:
On 3/31/2023 2:15 AM, VMSK wrote:
I am looking at a verilog code written by someone else . Below is the
snippet .

module test( ……. )
Input TMS,
`define STATE_1 4\'b0100
`define STATE_2 4\'b0101
reg [3:0] NxtState;
wire [3:0] CurState;

always @* begin
case (CurState[3:0])
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;
default : NxtState[3:0] = {4{1\'bx}};
endcase
End

endmodule



The is not the full code , I have just taken some parts of it to ask
question.
Wanted to understand what is happening in :
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;

Substituting the `defines:

4\'b0100 : NxtState[3:0] = TMS ? 4\'b0100 : 4\'b0101;

I believe this would translate in English to:

If CurState[3:0] = 4\'b0100 then
if NxtState{3:0] = TMS then 4\'b0100 = 4\'b0100, else 4\'b0100 = 4\'b0101.


This doesn\'t make any sense to me because the use of `define for STATE_1
and STATE_2 just means that the 4 bit binary will be replaced with the
defined value.

Charlie

Correction, I misread the whole thing:

It should be read as:
If CurState[3:0] = 4\'b0100 then
NxtState[3:0] = 4\'b0100 if TMS = 4\'b0100 else NxtState[3:0] = 4\'b0101.

Which makes more sense.

You have the selection expression a bit wrong. It would be
if (TMS) then
NxtState[3:0] = 4\'b0100 > else
NxtState[3:0] = 4\'b0101
Click to expand...

I believe we are saying the same thing except I gave TMS a value to test
for true. In other words:

if (TMS == 4\'b0100) then
NxtState[3:0] = 4\'b0100
else
NxtState[3:0] = 4\'b0101

> I don\'t recall exactly the values of TMS that equate to true and false for TMS, but I expect you get the idea.

His code just says TMS is an input.

I didn\'t read the code carefully enough to see the case statement.
Click to expand...

That\'s exactly what I did and why I had to correct myself. I hate when
I answer too quickly. Hopefully I didn\'t do it again.

I must be getting old or something.
Click to expand...

I am old.

Charlie


 
On Saturday, April 1, 2023 at 1:16:17 PM UTC-4, Charlie wrote:
On 4/1/2023 12:33 PM, gnuarm.del...@gmail.com wrote:
On Saturday, April 1, 2023 at 10:52:12 AM UTC-4, Charlie wrote:
On 4/1/2023 10:36 AM, Charlie wrote:
On 3/31/2023 2:15 AM, VMSK wrote:
I am looking at a verilog code written by someone else . Below is the
snippet .

module test( ……. )
Input TMS,
`define STATE_1 4\'b0100
`define STATE_2 4\'b0101
reg [3:0] NxtState;
wire [3:0] CurState;

always @* begin
case (CurState[3:0])
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;
default : NxtState[3:0] = {4{1\'bx}};
endcase
End

endmodule



The is not the full code , I have just taken some parts of it to ask
question.
Wanted to understand what is happening in :
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;

Substituting the `defines:

4\'b0100 : NxtState[3:0] = TMS ? 4\'b0100 : 4\'b0101;

I believe this would translate in English to:

If CurState[3:0] = 4\'b0100 then
if NxtState{3:0] = TMS then 4\'b0100 = 4\'b0100, else 4\'b0100 = 4\'b0101.


This doesn\'t make any sense to me because the use of `define for STATE_1
and STATE_2 just means that the 4 bit binary will be replaced with the
defined value.

Charlie

Correction, I misread the whole thing:

It should be read as:
If CurState[3:0] = 4\'b0100 then
NxtState[3:0] = 4\'b0100 if TMS = 4\'b0100 else NxtState[3:0] = 4\'b0101.

Which makes more sense.

You have the selection expression a bit wrong. It would be
if (TMS) then
NxtState[3:0] = 4\'b0100 > else
NxtState[3:0] = 4\'b0101

I believe we are saying the same thing except I gave TMS a value to test
for true. In other words:

if (TMS == 4\'b0100) then
NxtState[3:0] = 4\'b0100
else
NxtState[3:0] = 4\'b0101
Click to expand...

TMS is not clear as to what data type it is, but I\'m pretty sure it\'s not an array of bits. The code is simply testing it for true or false, not equality to a value.

TMS ? `STATE_1 : `STATE_2

The operator ? checks TMS for \"truth\"...


I don\'t recall exactly the values of TMS that equate to true and false for TMS, but I expect you get the idea.
His code just says TMS is an input.
Click to expand...

Yeah, Verilog has many, many situations where defaults apply, so TMS is whatever data type is the Verilog default in this case. This is one reason why I don\'t like Verilog. If you are not intimate with the defaults, you can get some very wrong results.


I didn\'t read the code carefully enough to see the case statement.
That\'s exactly what I did and why I had to correct myself. I hate when
I answer too quickly. Hopefully I didn\'t do it again.
I must be getting old or something.

I am old.
Click to expand...

Getting older is still better than the alternative...

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209
 
On 4/1/2023 2:47 PM, gnuarm.del...@gmail.com wrote:
On Saturday, April 1, 2023 at 1:16:17 PM UTC-4, Charlie wrote:
On 4/1/2023 12:33 PM, gnuarm.del...@gmail.com wrote:
On Saturday, April 1, 2023 at 10:52:12 AM UTC-4, Charlie wrote:
On 4/1/2023 10:36 AM, Charlie wrote:
On 3/31/2023 2:15 AM, VMSK wrote:
I am looking at a verilog code written by someone else . Below is the
snippet .

module test( ……. )
Input TMS,
`define STATE_1 4\'b0100
`define STATE_2 4\'b0101
reg [3:0] NxtState;
wire [3:0] CurState;

always @* begin
case (CurState[3:0])
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;
default : NxtState[3:0] = {4{1\'bx}};
endcase
End

endmodule



The is not the full code , I have just taken some parts of it to ask
question.
Wanted to understand what is happening in :
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;

Substituting the `defines:

4\'b0100 : NxtState[3:0] = TMS ? 4\'b0100 : 4\'b0101;

I believe this would translate in English to:

If CurState[3:0] = 4\'b0100 then
if NxtState{3:0] = TMS then 4\'b0100 = 4\'b0100, else 4\'b0100 = 4\'b0101.


This doesn\'t make any sense to me because the use of `define for STATE_1
and STATE_2 just means that the 4 bit binary will be replaced with the
defined value.

Charlie

Correction, I misread the whole thing:

It should be read as:
If CurState[3:0] = 4\'b0100 then
NxtState[3:0] = 4\'b0100 if TMS = 4\'b0100 else NxtState[3:0] = 4\'b0101.

Which makes more sense.

You have the selection expression a bit wrong. It would be
if (TMS) then
NxtState[3:0] = 4\'b0100 > else
NxtState[3:0] = 4\'b0101

I believe we are saying the same thing except I gave TMS a value to test
for true. In other words:

if (TMS == 4\'b0100) then
NxtState[3:0] = 4\'b0100
else
NxtState[3:0] = 4\'b0101

TMS is not clear as to what data type it is, but I\'m pretty sure it\'s not an array of bits. The code is simply testing it for true or false, not equality to a value.
Click to expand...

I see your point and I did figure that TMS was a 4 bit input and I
shouldn\'t have. It should probably be considered a one wire (1 bit)
input where TRUE is 1 and FALSE is anything else (0, x, or z).

TMS ? `STATE_1 : `STATE_2

The operator ? checks TMS for \"truth\"...
Click to expand...

Yes.

I don\'t recall exactly the values of TMS that equate to true and false for TMS, but I expect you get the idea.
His code just says TMS is an input.

Yeah, Verilog has many, many situations where defaults apply, so TMS is whatever data type is the Verilog default in this case. This is one reason why I don\'t like Verilog. If you are not intimate with the defaults, you can get some very wrong results.


I didn\'t read the code carefully enough to see the case statement.
That\'s exactly what I did and why I had to correct myself. I hate when
I answer too quickly. Hopefully I didn\'t do it again.
I must be getting old or something.

I am old.

Getting older is still better than the alternative...
Click to expand...

:)

Charlie





 
On Sunday, April 2, 2023 at 1:17:54 AM UTC+5:30, Charlie wrote:
On 4/1/2023 2:47 PM, gnuarm.del...@gmail.com wrote:
On Saturday, April 1, 2023 at 1:16:17 PM UTC-4, Charlie wrote:
On 4/1/2023 12:33 PM, gnuarm.del...@gmail.com wrote:
On Saturday, April 1, 2023 at 10:52:12 AM UTC-4, Charlie wrote:
On 4/1/2023 10:36 AM, Charlie wrote:
On 3/31/2023 2:15 AM, VMSK wrote:
I am looking at a verilog code written by someone else . Below is the
snippet .

module test( ……. )
Input TMS,
`define STATE_1 4\'b0100
`define STATE_2 4\'b0101
reg [3:0] NxtState;
wire [3:0] CurState;

always @* begin
case (CurState[3:0])
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;
default : NxtState[3:0] = {4{1\'bx}};
endcase
End

endmodule



The is not the full code , I have just taken some parts of it to ask
question.
Wanted to understand what is happening in :
`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;

Substituting the `defines:

4\'b0100 : NxtState[3:0] = TMS ? 4\'b0100 : 4\'b0101;

I believe this would translate in English to:

If CurState[3:0] = 4\'b0100 then
if NxtState{3:0] = TMS then 4\'b0100 = 4\'b0100, else 4\'b0100 = 4\'b0101.


This doesn\'t make any sense to me because the use of `define for STATE_1
and STATE_2 just means that the 4 bit binary will be replaced with the
defined value.

Charlie

Correction, I misread the whole thing:

It should be read as:
If CurState[3:0] = 4\'b0100 then
NxtState[3:0] = 4\'b0100 if TMS = 4\'b0100 else NxtState[3:0] = 4\'b0101.

Which makes more sense.

You have the selection expression a bit wrong. It would be
if (TMS) then
NxtState[3:0] = 4\'b0100 > else
NxtState[3:0] = 4\'b0101

I believe we are saying the same thing except I gave TMS a value to test
for true. In other words:

if (TMS == 4\'b0100) then
NxtState[3:0] = 4\'b0100
else
NxtState[3:0] = 4\'b0101

TMS is not clear as to what data type it is, but I\'m pretty sure it\'s not an array of bits. The code is simply testing it for true or false, not equality to a value.
I see your point and I did figure that TMS was a 4 bit input and I
shouldn\'t have. It should probably be considered a one wire (1 bit)
input where TRUE is 1 and FALSE is anything else (0, x, or z).

TMS ? `STATE_1 : `STATE_2

The operator ? checks TMS for \"truth\"...

Yes.

I don\'t recall exactly the values of TMS that equate to true and false for TMS, but I expect you get the idea.
His code just says TMS is an input.

Yeah, Verilog has many, many situations where defaults apply, so TMS is whatever data type is the Verilog default in this case. This is one reason why I don\'t like Verilog. If you are not intimate with the defaults, you can get some very wrong results.


I didn\'t read the code carefully enough to see the case statement.
That\'s exactly what I did and why I had to correct myself. I hate when
I answer too quickly. Hopefully I didn\'t do it again.
I must be getting old or something.

I am old.

Getting older is still better than the alternative...

:)

Charlie
Click to expand...

Thanks Charlie and gnuarm.del...@gmail.com . In the code i am seeing , TMS is a single bit input . Thanks again for the discussion.

`STATE_1 : NxtState[3:0] = TMS ? `STATE_1 : `STATE_2 ;

In the above line : NxtState[3:0] will get assigned with `STATE_1 if TMS is 1 . Else , if TMS is (0, X, Z) it will get assigned `STATE_2 .

Thanks again
 
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